In an electronic switching system (ESS) comprising a large number of processors, use of a hierarchical processor architecture is gaining popularity. For example, an access switching subsystem performing such functions as scanning, interfacing and time switching, included in the ESS, has the hierarchical processor architecture. In the hierarchical processor architecture of the access switching subsystem, the functions of processors are divided into, e.g., two hierarchies, upper and lower. The upper hierarchical function is performed by a main processor (MP), whereas the lower hierarchical function is performed by a peripheral processor (PP).
The PP, as is well know in the art, performs simple processing operations, such as supervising telephony devices, e.g., a subscriber/trunk interface device and a signaling device, and controlling system peripheral devices, e.g., a magnetic tape driver, a disk driver and a CRT (cathode ray tube) terminal. For instance, the scanning of the subscriber's hook-off and signal distribution function are handled by the PP. On the other hand, the MP controls the PP to perform call processing and OA&M (operation, administration and maintenance).
To transmit data between the PP and each of the devices, in such a hierarchical architecture, it is necessary to establish a data communications path therebetween. In the access switching subsystem, it is known that a HIT (HDLC(high level data link control) interface time slot) communications processor is used as the data communications path for the efficient data transmission. The HIT communications processor has a master and slave configuration which employs one master processor and three slave processors, each supporting a TDM (time division-multiplexed) interface using an E1/CEPT mode of Europe and being associated with 16 devices.
In addition, there is incorporated a storage device to interface the PP to each of the devices and convey voice messages and/or data and command and status data therebetween. A dual port random access memory (DPRAM) that is relatively expensive is employed as the storage device for storing the data, wherein the DPRAM is composed of a plurality of buffers and has the capacity of storing data of 64 Kbytes. The buffers are classified into two types, i.e., a TX buffer and a RX buffer. On the other hand, most data being communicated between the PP and each of the devices is data related to general call processing whose length is less than 64 bytes. Data excluding the above data is data for call processing related to a signaling number 7 and an integrated service digital network (ISDN), wherein the length of the other data is 500 bytes whose head information is of 8 bytes. In the prior art DPRAM architecture, there are assigned 128 buffers, i.e., 64 TX buffers and 64 RX buffers, each buffer being capable of accommodating data of 508 bytes. Using such a hardware arrangement, the data between the PP and each of the devices can be communicated.
However, in the conventional hierarchical architecture employing a DPRAM, it is designed that one device can communicate with only one buffer and, therefore, it is impossible to store additional data onto the buffer until it is completely cleared, which may result in a communications interrupt between the PP and each of the devices.